1. Field of the Invention
The present invention relates to a non-volatile ferroelectric cell array circuit, and more particular to a non-volatile ferroelectric cell array circuit which can reduce a cell size and improve operational characteristics, by using a double bit line sensing structure for inducing a sensing voltage of a main bit line by using a current gain according to a cell data, and using a PNPN diode as a switch device of a memory cell.
2. Description of the Background Art
A non-volatile ferroelectric memory, namely, a ferroelectric random access memory (FeRAM) has a data processing speed similar to that of a dynamic random access memory (DRAM), and preserves data even in power off. Therefore, the FeRAM is expected as a next generation memory.
The FeRAM has an extremely-similar structure to that of the DRAM, and utilizes high residual polarization which is a property of a ferroelectric by using the ferroelectric as a material of a capacitor. Even when an electric field is removed, data can be preserved by the residual polarization.
Recently, a capacity of the non-volatile ferroelectric memory is increased to a megabyte or gigabyte level. As the capacity of the memory increases, a cell size needs to decrease. However, if the cell size decreases, a cell capacitance also decreases. In order to stably operate the memory, a capacitance of a bit line must be reduced. It is not easy to reduce the capacitance of the bit line in a high integration memory. In addition, an interval between the bit lines is small in the high integration memory. As a result, unnecessary power consumption may be caused by short channels in a cell structure using an NMOS transistor.